JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs

Descripción del Articulo

Poster presented at the 2021 CEDAR Virtual Workshop, June 20-25.
Detalles Bibliográficos
Autores: Verastegui, J., Rojas, J., Tupac, I., Caceres, D., Gonzales, L.
Formato: objeto de conferencia
Fecha de Publicación:2021
Institución:Instituto Geofísico del Perú
Repositorio:IGP-Institucional
Lenguaje:inglés
OAI Identifier:oai:repositorio.igp.gob.pe:20.500.12816/4964
Enlace del recurso:http://hdl.handle.net/20.500.12816/4964
Nivel de acceso:acceso abierto
Materia:Acquisition System
FPGA
JESD204B
PCB design
HDL design
https://purl.org/pe-repo/ocde/ford#1.05.01
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dc.title.es_ES.fl_str_mv JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
title JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
spellingShingle JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
Verastegui, J.
Acquisition System
FPGA
JESD204B
PCB design
HDL design
https://purl.org/pe-repo/ocde/ford#1.05.01
title_short JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
title_full JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
title_fullStr JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
title_full_unstemmed JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
title_sort JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
author Verastegui, J.
author_facet Verastegui, J.
Rojas, J.
Tupac, I.
Caceres, D.
Gonzales, L.
author_role author
author2 Rojas, J.
Tupac, I.
Caceres, D.
Gonzales, L.
author2_role author
author
author
author
dc.contributor.author.fl_str_mv Verastegui, J.
Rojas, J.
Tupac, I.
Caceres, D.
Gonzales, L.
dc.subject.es_ES.fl_str_mv Acquisition System
FPGA
JESD204B
PCB design
HDL design
topic Acquisition System
FPGA
JESD204B
PCB design
HDL design
https://purl.org/pe-repo/ocde/ford#1.05.01
dc.subject.ocde.es_ES.fl_str_mv https://purl.org/pe-repo/ocde/ford#1.05.01
description Poster presented at the 2021 CEDAR Virtual Workshop, June 20-25.
publishDate 2021
dc.date.accessioned.none.fl_str_mv 2021-07-09T13:27:42Z
dc.date.available.none.fl_str_mv 2021-07-09T13:27:42Z
dc.date.issued.fl_str_mv 2021-06
dc.type.es_ES.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
dc.identifier.uri.none.fl_str_mv http://hdl.handle.net/20.500.12816/4964
url http://hdl.handle.net/20.500.12816/4964
dc.language.iso.es_ES.fl_str_mv eng
language eng
dc.rights.es_ES.fl_str_mv info:eu-repo/semantics/openAccess
dc.rights.uri.es_ES.fl_str_mv https://creativecommons.org/licenses/by-nc-nd/4.0/
eu_rights_str_mv openAccess
rights_invalid_str_mv https://creativecommons.org/licenses/by-nc-nd/4.0/
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dc.publisher.es_ES.fl_str_mv Instituto Geofísico del Perú
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instname:Instituto Geofísico del Perú
instacron:IGP
instname_str Instituto Geofísico del Perú
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institution IGP
reponame_str IGP-Institucional
collection IGP-Institucional
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spelling Verastegui, J.Rojas, J.Tupac, I.Caceres, D.Gonzales, L.2021-07-09T13:27:42Z2021-07-09T13:27:42Z2021-06http://hdl.handle.net/20.500.12816/4964Poster presented at the 2021 CEDAR Virtual Workshop, June 20-25.The latest data acquisition system running at the Jicamarca Radio Observatory for the main radar has been used for more than five years now. Although there are no major inconveniences on the performance there have been some problems with internal interferences which are usually unpredictable and related to the PCB design, the noise floor can be different between channels too. So there are some chances of improvement developing a new approach. We propose a new design based on a high speed JESD204B data interface; the digital signal processing and custom acquisition logic will be implemented inside an FPGA capable of managing the JESD204B high-speed interface. This will give us the flexibility of implementing digital blocks inside the FPGA to improve the performance of the receivers, we will gain scalability to perform on a much higher bandwidth and the PCB will be very much simplified which will reduce the manufacturing costs, design time, and development time.application/pdfengInstituto Geofísico del Perúinfo:eu-repo/semantics/openAccesshttps://creativecommons.org/licenses/by-nc-nd/4.0/Acquisition SystemFPGAJESD204BPCB designHDL designhttps://purl.org/pe-repo/ocde/ford#1.05.01JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAsinfo:eu-repo/semantics/conferenceObjectreponame:IGP-Institucionalinstname:Instituto Geofísico del Perúinstacron:IGPORIGINALPoster_Verastegui_et_al_2021.pdfPoster_Verastegui_et_al_2021.pdfapplication/pdf1030631https://repositorio.igp.gob.pe/bitstreams/2b63045f-c2b0-4ed6-b6d7-ff80a1b0b6a1/downloade3baeb4f8be3237d1e84f18597d015d1MD51LICENSElicense.txtlicense.txttext/plain; charset=utf-81748https://repositorio.igp.gob.pe/bitstreams/300600cf-37fd-4ffe-9f4b-a2c3d3461da8/download8a4605be74aa9ea9d79846c1fba20a33MD52TEXTPoster_Verastegui_et_al_2021.pdf.txtPoster_Verastegui_et_al_2021.pdf.txtExtracted texttext/plain4130https://repositorio.igp.gob.pe/bitstreams/41e9a3cb-5646-4ebf-a0b0-9aa1adabaa2b/download06de991e1a6e9e2b1ce8c3c27ae59d2cMD53THUMBNAILPoster_Verastegui_et_al_2021.pdf.jpgPoster_Verastegui_et_al_2021.pdf.jpgIM Thumbnailimage/jpeg134064https://repositorio.igp.gob.pe/bitstreams/ca4898b4-cbde-406a-8849-2adf79735832/download8935239f7c8d1e19a51c9ba24d26f64fMD5420.500.12816/4964oai:repositorio.igp.gob.pe:20.500.12816/49642021-07-09 14:40:59.504https://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/openAccessopen.accesshttps://repositorio.igp.gob.peRepositorio Geofísico del Perudspace-help@myu.eduTk9URTogUExBQ0UgWU9VUiBPV04gTElDRU5TRSBIRVJFClRoaXMgc2FtcGxlIGxpY2Vuc2UgaXMgcHJvdmlkZWQgZm9yIGluZm9ybWF0aW9uYWwgcHVycG9zZXMgb25seS4KCk5PTi1FWENMVVNJVkUgRElTVFJJQlVUSU9OIExJQ0VOU0UKCkJ5IHNpZ25pbmcgYW5kIHN1Ym1pdHRpbmcgdGhpcyBsaWNlbnNlLCB5b3UgKHRoZSBhdXRob3Iocykgb3IgY29weXJpZ2h0Cm93bmVyKSBncmFudHMgdG8gRFNwYWNlIFVuaXZlcnNpdHkgKERTVSkgdGhlIG5vbi1leGNsdXNpdmUgcmlnaHQgdG8gcmVwcm9kdWNlLAp0cmFuc2xhdGUgKGFzIGRlZmluZWQgYmVsb3cpLCBhbmQvb3IgZGlzdHJpYnV0ZSB5b3VyIHN1Ym1pc3Npb24gKGluY2x1ZGluZwp0aGUgYWJzdHJhY3QpIHdvcmxkd2lkZSBpbiBwcmludCBhbmQgZWxlY3Ryb25pYyBmb3JtYXQgYW5kIGluIGFueSBtZWRpdW0sCmluY2x1ZGluZyBidXQgbm90IGxpbWl0ZWQgdG8gYXVkaW8gb3IgdmlkZW8uCgpZb3UgYWdyZWUgdGhhdCBEU1UgbWF5LCB3aXRob3V0IGNoYW5naW5nIHRoZSBjb250ZW50LCB0cmFuc2xhdGUgdGhlCnN1Ym1pc3Npb24gdG8gYW55IG1lZGl1bSBvciBmb3JtYXQgZm9yIHRoZSBwdXJwb3NlIG9mIHByZXNlcnZhdGlvbi4KCllvdSBhbHNvIGFncmVlIHRoYXQgRFNVIG1heSBrZWVwIG1vcmUgdGhhbiBvbmUgY29weSBvZiB0aGlzIHN1Ym1pc3Npb24gZm9yCnB1cnBvc2VzIG9mIHNlY3VyaXR5LCBiYWNrLXVwIGFuZCBwcmVzZXJ2YXRpb24uCgpZb3UgcmVwcmVzZW50IHRoYXQgdGhlIHN1Ym1pc3Npb24gaXMgeW91ciBvcmlnaW5hbCB3b3JrLCBhbmQgdGhhdCB5b3UgaGF2ZQp0aGUgcmlnaHQgdG8gZ3JhbnQgdGhlIHJpZ2h0cyBjb250YWluZWQgaW4gdGhpcyBsaWNlbnNlLiBZb3UgYWxzbyByZXByZXNlbnQKdGhhdCB5b3VyIHN1Ym1pc3Npb24gZG9lcyBub3QsIHRvIHRoZSBiZXN0IG9mIHlvdXIga25vd2xlZGdlLCBpbmZyaW5nZSB1cG9uCmFueW9uZSdzIGNvcHlyaWdodC4KCklmIHRoZSBzdWJtaXNzaW9uIGNvbnRhaW5zIG1hdGVyaWFsIGZvciB3aGljaCB5b3UgZG8gbm90IGhvbGQgY29weXJpZ2h0LAp5b3UgcmVwcmVzZW50IHRoYXQgeW91IGhhdmUgb2J0YWluZWQgdGhlIHVucmVzdHJpY3RlZCBwZXJtaXNzaW9uIG9mIHRoZQpjb3B5cmlnaHQgb3duZXIgdG8gZ3JhbnQgRFNVIHRoZSByaWdodHMgcmVxdWlyZWQgYnkgdGhpcyBsaWNlbnNlLCBhbmQgdGhhdApzdWNoIHRoaXJkLXBhcnR5IG93bmVkIG1hdGVyaWFsIGlzIGNsZWFybHkgaWRlbnRpZmllZCBhbmQgYWNrbm93bGVkZ2VkCndpdGhpbiB0aGUgdGV4dCBvciBjb250ZW50IG9mIHRoZSBzdWJtaXNzaW9uLgoKSUYgVEhFIFNVQk1JU1NJT04gSVMgQkFTRUQgVVBPTiBXT1JLIFRIQVQgSEFTIEJFRU4gU1BPTlNPUkVEIE9SIFNVUFBPUlRFRApCWSBBTiBBR0VOQ1kgT1IgT1JHQU5JWkFUSU9OIE9USEVSIFRIQU4gRFNVLCBZT1UgUkVQUkVTRU5UIFRIQVQgWU9VIEhBVkUKRlVMRklMTEVEIEFOWSBSSUdIVCBPRiBSRVZJRVcgT1IgT1RIRVIgT0JMSUdBVElPTlMgUkVRVUlSRUQgQlkgU1VDSApDT05UUkFDVCBPUiBBR1JFRU1FTlQuCgpEU1Ugd2lsbCBjbGVhcmx5IGlkZW50aWZ5IHlvdXIgbmFtZShzKSBhcyB0aGUgYXV0aG9yKHMpIG9yIG93bmVyKHMpIG9mIHRoZQpzdWJtaXNzaW9uLCBhbmQgd2lsbCBub3QgbWFrZSBhbnkgYWx0ZXJhdGlvbiwgb3RoZXIgdGhhbiBhcyBhbGxvd2VkIGJ5IHRoaXMKbGljZW5zZSwgdG8geW91ciBzdWJtaXNzaW9uLgo=
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JRO digital receiver modernization using ADCs with high-speed JESD204B data interface and FPGAs
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