Study: A scanlet for testing and updating designs intended for the verification of fuzzy logic controllers

• Autores: Córdova Sosa, Luis, Paz Campaña, José, Egoávil Retamozo, Jorge
• Formato: artículo
• Fecha de Publicación: 2000
• Institución: Universidad Nacional de Ingeniería
• Repositorio: Revistas - Universidad Nacional de Ingeniería
• Lenguaje: español
• OAI Identifier: oai:oai:revistas.uni.edu.pe:article/466
• Enlace del recurso: https://revistas.uni.edu.pe/index.php/tecnia/article/view/466
• Nivel de acceso: acceso abierto
• Materia: Scanlet; ATPG; JAVA API for Boundary-Scan; Fuzzy Logic; Functional Verification

This article presents preliminary work on the implementation of a Scanlet for: (a) automatic checking of pattern generation related to digital circuits based on amodel with interruption in the presence of failure, (b) in situ monitoring and debugging, (c) update ofthe architecture of a fuzzy logic controller, and (d) pin-level fault injection using JavaAPI. Points (a)-(c) are verification tasks. As a first approximation, the STUD system has been developed using the (built-in) JTAG (Joint Test Action Group) architecture and configured by a CPLD for testing and programming operations. Meanwhile, the operations are executed by Scanlet, which can be run from an Internet page. Finally, a fuzzy logic controller, like an IP core, is used as a trademark.