A lowpower recording system for intracortical signal acquisition based on design specification relaxation and lower bandwidth filtering

• Autor: Vitón Zorrilla, Luighi Anthony
• Formato: tesis de maestría
• Fecha de Publicación: 2023
• Institución: Pontificia Universidad Católica del Perú
• Repositorio: PUCP-Tesis
• Lenguaje: inglés
• OAI Identifier: oai:tesis.pucp.edu.pe:20.500.12404/26838
• Enlace del recurso: http://hdl.handle.net/20.500.12404/26838
• Nivel de acceso: acceso abierto
• Materia: Interfaces de usuarios (Computación); Procesamiento de señales biomédicas; Redes neuronales (Computación); https://purl.org/pe-repo/ocde/ford#2.00.00

In this thesis, we designed and evaluated a circuit model at the transistor level of a low-resolution and low bandwidth ADC (analog-to-digital converter) with level-crossing architecture (LCADC), used as part of the acquisition chain of a BCI (brain-to-computer interface) device. The aim is to obtain minimal specifications that could return adequate levels of accuracy at spike detection and reduce power dissipation. In addition, we included a NEO preprocessor in the test to help in the detection accuracy. To achieve the objectives proposed, we started developing a software model for the preprocessor and the ADCs to evaluate the different variations of resolution, bandwidth, noise level, and NEO window. After finding the desired minimum values, we continued with the hardware development of the ADC. We designed the level crossing architecture and a conventional SAR to have a reference against which we compare the LCADC performance. After that, we developed a NEO circuit and applied synthesized neural recordings to evaluate power consumption with the ADC. Additionally, we designed a conventional analog frontend to estimate the power for the band of interest. Also, we estimated the dissipation for wireless transmission by calculating the approximated data stream expected in the level-crossing sampling scheme. Summing them, we obtained the power consumption of the complete acquisition chain. In conclusion, although reducing the intrinsic power of the LCADC is challenging, the scheme helps reduce the total power consumption of the acquisition chain with adequate accuracy, making it competitive against currently reported BCI devices.