In this thesis, we designed and evaluated a circuit model at the transistor level of a low-resolution and low bandwidth ADC (analog-to-digital converter) with level-crossing architecture (LCADC), used as part of the acquisition chain of a BCI (brain-to-computer interface) device. The aim is to obtain minimal specifications that could return adequate levels of accuracy at spike detection and reduce power dissipation. In addition, we included a NEO preprocessor in the test to help in the detection accuracy. To achieve the objectives proposed, we started developing a software model for the preprocessor and the ADCs to evaluate the different variations of resolution, bandwidth, noise level, and NEO window. After finding the desired minimum values, we continued with the hardware development of the ADC. We designed the level crossing architecture and a conventional SAR to have a reference agai...

El objetivo de la tesis "Modelamiento e implementación de un sistema de sensado de pH de bajo consumo de energía aplicado al control de calidad de agua de ríos", es el desarrollo de un sistema de sensado de pH de bajo consumo de energía el cual tenga como fin su incorporación a una red de sensores inalámbrica. El pH es una medida operacional muy importante en cuanto sus variaciones son indicadores de cambios en la composición del agua con efectos nocivos para los ecosistemas que viven y hacen uso de ésta, empleándose sistemas de sensado remotos para detectar estas variaciones. No obstante, los sistemas basados en sensores y técnicas convencionales usualmente tienen un elevado consumo de energía, lo cual implica tiempos reducidos de autonomía. Es por ello por lo que en la tesis se realiza la selección de una tecnología de sensado de bajo consumo a la vez que se efectúa la i...

In this thesis, we designed and evaluated a circuit model at the transistor level of a low-resolution and low bandwidth ADC (analog-to-digital converter) with level-crossing architecture (LCADC), used as part of the acquisition chain of a BCI (brain-to-computer interface) device. The aim is to obtain minimal specifications that could return adequate levels of accuracy at spike detection and reduce power dissipation. In addition, we included a NEO preprocessor in the test to help in the detection accuracy. To achieve the objectives proposed, we started developing a software model for the preprocessor and the ADCs to evaluate the different variations of resolution, bandwidth, noise level, and NEO window. After finding the desired minimum values, we continued with the hardware development of the ADC. We designed the level crossing architecture and a conventional SAR to have a reference agai...