Design of a DVB-S2 compliant LDPC decoder for FPGA

• Autor: Montaño Gamarra, Guillermo Daniel
• Formato: tesis de grado
• Fecha de Publicación: 2021
• Institución: Pontificia Universidad Católica del Perú
• Repositorio: PUCP-Tesis
• Lenguaje: inglés
• OAI Identifier: oai:tesis.pucp.edu.pe:20.500.12404/20414
• Enlace del recurso: http://hdl.handle.net/20.500.12404/20414
• Nivel de acceso: acceso abierto
• Materia: Códigos de corrección (Teoría de la información); Algoritmos--Aplicaciones; Televisión digital; https://purl.org/pe-repo/ocde/ford#2.02.01

Low Density Parity Check codes presents itself as the dominant FEC code in terms of performance, having the nearest performance to the Shannon limit and proving its usefulness in the increasing range of applications and standards that already used it. Low power devices are not except of this rapid development, where it emerges the necessity of decoders of low power without totally sacrificing performance or resource usage. The present work details the devolopment of a LDPC decoder compliant with the DVB-S2 standard for digital television, motivated for its already established use in uplink and downlink satellite applications and its great performance at large code lengths. This research presents the study of the min-sum algorithm and the design of the elements that conform the core decoder, including both functional units (variable and check nodes), memory blocks and routing network. In the context of DVB-S2, it focused exclusively in the prototyping of the inner LDPC decoder and targets FPGA as platform. A variety of design strategies are applied in the design of the core, including the optimal selection of the architecture and the schedule policy, the design of the control unit as a Algorithmic State Machine (ASM) and the inclusion of specialized modules to reduce the number of clock cycles per decoding process, such as early stopping. The selected features for this work are code length of 64800 bits and code rate equal to 1/2. The selected architecture is partially parallel with flooding schedule and operates over binary symbols (Galois field GF(2)). For testing, it assumes a channel with AWGN and BPSK modulation, so the demodulator feeds soft decision information of each symbol based on both assumptions. The design has been validated using different verification methodologies according to complexity and predictability of each part or the whole system. Obtained results show the decoder, when configured for a maximum of 10 iterations, has a BER performance of 10-3 at a SNR of 2 dB, having an advantage of 1 dB respect to previous published Works [1]. It uses 60363 slice LUT and 23552 slice registers when synthesized in the Virtex 7 xc7vx550t FPGA from Xilinx, a reduction of 10% in resource usage from [1]. It achieves a maximum frequency operation of 194 Mhz and a throughput of 142.99 Mbps at worst case. The top energy per bit rate is 18.344 nJ/bit.