This article aims to work with PROTEUS and the Cyclone II FPGA to design a 3-bit counter circuit in software and hardware. For the software part, PROTEUS will be used, and it comes with the GAL22v10, a reprogrammable CPLD manufactured by the company Lattice Semiconductors. The VHDL description will be made using the Cypress Warp Galaxy software, it generates a .jed file from the constructed VHDL file, the .jed file is used to record it in the GAL and thus be able to simulate the description made. The Galaxy software is free to use and a virtual machine is required because it works with Windows XP. Virtual Box will be used as Virtualization software belonging to the ORACLE company. Regarding the FPGA, the cyclone II ep2ct144c8n from the INTEL FPGA company will be used. Which will be programmed with the Quartus II 13.0 sp1 software. As a result, the circuit will be simulated in PROTEUS wit...